Sixteen years after RISC-V emerged from a Berkeley lab, the open instruction set has landed one of its most practical software wins yet. CPython, the reference implementation of Python, now officially supports the RISC-V CPU architecture. The announcement arrives at the same time SiFive is shipping BigSky, a 2U rackable server with 32 P870-D cores and NVIDIA CUDA running on the platform.
TL;DR: CPython, the reference implementation of Python, has officially added support for the RISC-V open CPU instruction set, lowering the barrier for software on the architecture. The move lands as RISC-V turns sixteen and SiFive ships a 2U rackable server with 32 P870-D cores and NVIDIA CUDA support.
What Did CPython Actually Add for RISC-V?
CPython, the reference implementation of the Python programming language, has officially added support for the RISC-V CPU instruction set, as reported by PBX Science. This means the interpreter’s build and test infrastructure now recognizes RISC-V as a supported target, rather than treating it as an experimental or community-maintained port.
Why does that distinction matter? Before official support, developers wanting to run Python on RISC-V hardware had to rely on unofficial builds, distribution-specific patches, or cross-compilation workflows with no guarantee of correctness. An official port brings the architecture into CPython’s regular testing cycle. Bugs specific to RISC-V get tracked upstream instead of silently ignored.
The practical effect is straightforward. Anyone deploying Python applications on RISC-V systems — from embedded controllers to servers — can expect the interpreter to compile and behave predictably. That predictability is exactly what software teams need before committing to a new architecture.
It also sends a signal. When the world’s most popular scripting language officially supports an ISA, downstream projects take notice. Packaging tools, CI pipelines, and library maintainers tend to follow the reference implementation’s lead. Python’s arrival makes RISC-V a less lonely place to build software.
Why Does Official Interpreter Support Matter for an Instruction Set?
Software ecosystems decide architecture wars, not raw hardware specs. An instruction set can be technically elegant and royalty-free, but without a mature toolchain and runtime support, developers simply walk away. Official CPython support removes one of the most common friction points.
Consider the typical developer workflow. A team evaluating RISC-V hardware for a product or a datacenter workload will check, almost immediately, whether their language runtime works. Python sits at the center of scripting, data processing, and AI tooling. If Python runs officially, thousands of dependent packages become plausible targets for porting and testing.
The timing amplifies the impact. SiFive has introduced BigSky, a rackable 2U RISC-V datacenter development server powered by 32 P870-D cores, with enterprise Linux support and NVIDIA CUDA now running on the platform, according to Converge Digest. The Register reports the system is intended for software porting and workload optimization, aiming to bring the open standard into the bitbarn.
So the pieces are aligning from both directions. Hardware vendors are shipping rackable machines, and language runtimes are adding official support. CUDA targeting RISC-V, discussed at Hot Chips 2026 by Chips and Cheese, adds a third layer: GPU compute frameworks eyeing the ISA. Each layer makes the next one easier to justify.
There is also a long-tail effect worth understanding. Embedded and IoT developers frequently prototype in Python before optimizing in C. As EE News Europe notes, one of RISC-V’s key advantages is the ability to add custom instructions to a core. A working Python interpreter lets engineers explore that customization without abandoning their preferred tooling.
How Has RISC-V Evolved Since Berkeley, According to Hot Chips 2026?
RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers, as Semiwiki’s coverage of Hot Chips 2026 explains. The architecture is now sixteen years old, and its trajectory has shifted from academic curiosity to industrial infrastructure.
The early appeal was modularity. RISC-V defined a small base integer instruction set plus optional extensions, letting designers build exactly the CPU they needed. That flexibility powered its adoption in microcontrollers and custom accelerators, where ARM licensing costs and x86 lock-in made little sense.
Hot Chips 2026 shows how the story has matured. The industry conversation has moved from modular ISA design toward standardized platforms — coherent profiles that let operating systems and software target RISC-V systems without per-vendor porting work. Standardization is what turns a collection of compatible-ish chips into a real platform.
The server segment is the clearest evidence. SiFive’s BigSky, covered by The Register, is explicitly designed to pull RISC-V into the datacenter, giving software teams real iron for porting and optimization. NVIDIA’s interest in supporting CUDA on RISC-V, per Chips and Cheese, signals that even GPU-centric compute stacks are treating the ISA as a serious target rather than a hobbyist curiosity.
Which RISC-V Hardware Can You Run Python on Today?
The hardware landscape is broader than most developers assume. RISC-V silicon now spans handheld dev boards, affordable desktops, and rack-mounted servers. Here is where an officially supported CPython can actually run:
- SiFive BigSky — a 2U rackable development server with 32 P870-D cores, enterprise Linux support, and NVIDIA CUDA running on the platform (Converge Digest).
- KEO AI PC — an affordable AI-enabled personal computer built around the open RISC-V architecture, Ubuntu Linux, and open-source software (Open Source For You).
- LilyGo K230 Kit — a mobile RISC-V handheld mini system with an optional keyboard and LoRa support for off-grid communication without Wi-Fi or cellular networks (Notebookcheck).
- Embedded custom cores — RISC-V processors with custom extensions for high-performance embedded computing, as described by EE News Europe.
- Development boards from various vendors — community hardware that previously depended on unofficial Python builds.
| Hardware | Form Factor | Notable Capability | Target Audience |
|---|---|---|---|
| SiFive BigSky | 2U rack server | 32 P870-D cores, CUDA support | Datacenter developers |
| KEO AI PC | Desktop PC | Ubuntu Linux, open-source stack | Budget-conscious users |
| LilyGo K230 | Handheld | Keyboard option, LoRa connectivity | Mobile and off-grid use |
| Custom embedded cores | Chip-level | User-defined instruction extensions | Embedded engineers |
The spread matters. A language port is only useful if hardware exists to run it, and RISC-V hardware now covers nearly every computing niche. From a pocket-sized LoRa handheld to a CUDA-capable rack server, Python developers have real targets today. The ecosystem is no longer theoretical.
Is RISC-V Ready for the Datacenter?
RISC-V is taking its first serious steps into the datacenter, and the hardware is finally rackable. SiFive introduced BigSky, a 2U rack-mount development server powered by 32 P870-D cores, with enterprise Linux support and NVIDIA CUDA running on the platform. That is a development machine, not a hyperscale production fleet. But it signals real intent.
The Register reported that the system is intended for software porting and workload optimization, designed to bring the open standard into the “bitbarn.” Semiwiki’s coverage of Hot Chips 2026 framed RISC-V’s evolution from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. The keyword is emerging.
So is the ecosystem ready? For porting and validation work, yes. For mission-critical production at scale, operators will want mature firmware, broad enterprise software certification, and a track record of uptime. CPython support removes one more excuse. Software stacks are catching up faster than many expected.
What Role Does CUDA Play in RISC-V’s Expansion?
CUDA is arguably the single most important software framework in GPU compute, and NVIDIA is now targeting RISC-V with it. Chips and Cheese reported from Hot Chips 2026 that NVIDIA is looking at supporting CUDA on RISC-V — though, as the author dryly noted, terms and conditions may apply. The significance is hard to miss.
Why does this matter so much? Because datacenter adoption historically dies without accelerator software. SiFive’s BigSky server already demonstrates CUDA running on the platform, per Converge Digest. That means a RISC-V development server can host familiar GPU-accelerated workflows rather than demanding a full software rewrite.
For Python developers, the connection is direct. If CUDA tooling lands on RISC-V, libraries like the PyTorch and NumPy ecosystem become portable to open-ISA servers. NVIDIA gains leverage in negotiations with ARM, and RISC-V gains credibility. Everyone has an incentive here.
How Do Custom Extensions Fit Into the RISC-V Ecosystem?
Custom instructions are simultaneously RISC-V’s greatest advantage and its hardest problem. EE News Europe describes the ability to add custom instructions as a key advantage and challenge of the architecture. Adding instructions to a RISC-V core can accelerate specific workloads dramatically — but fragmentation lurks behind every extension.
The risk is well known in the industry. If every vendor ships incompatible extensions, software compiled for one chip may not run on another. That undermines the portability that makes an open ISA attractive in the first place. Semiwiki’s Hot Chips 2026 coverage points to the countermeasure: standardized platforms layered on top of the modular ISA, so that software targets a known profile rather than a bespoke core.
CPython’s official support helps here too. A reference implementation that builds and runs across RISC-V profiles gives extension authors a stable baseline. Custom silicon can shine below, while standard software stays portable above. That balance defines the ecosystem’s future.
What Does the KEO Board Mean for Affordable RISC-V Desktops?
KEO is an affordable AI-enabled personal computer built around the open RISC-V architecture, Ubuntu Linux, and open-source software, as reported by Open Source For You. In other words, it is a genuine desktop-class attempt at open hardware rather than a developer board masquerading as one. That distinction matters for adoption.
The KEO targets the “affordable AI PC” category, pairing RISC-V silicon with Ubuntu and an open-source software stack. For students, hobbyists, and privacy-minded users, it offers a fully inspectable computing stack from ISA upward. It is not a gaming rig. It is a statement about ownership.
There is also a broader hobbyist wave. Notebookcheck covered the LilyGo K230, a RISC-V mini system with an optional keyboard and LoRa support for off-grid communication without Wi-Fi or cellular networks. From handhelds to desktops, the price floor keeps dropping. Cheap hardware plus official CPython support equals a low barrier to experimentation.
Should Developers Port Their Python Code to RISC-V Now?
For most teams, the honest answer is: start evaluating, but don’t bet production on it yet. CPython now officially supports the RISC-V instruction set, per PBXScience, so the reference interpreter builds and runs on the architecture. That removes the biggest practical blocker for pure-Python code.
The Register’s reporting on BigSky suggests the intended workflow is exactly this: porting software and optimizing workloads on development hardware before any production commitment. Teams with C extensions will need to verify that native dependencies compile cleanly for RISC-V. Teams doing embedded or edge work should move faster.
A reasonable path looks like this:
- Verify your CI pipeline can cross-compile for RISC-V
- Test pure-Python services first, since CPython support is official
- Audit C/C++ extensions and native wheels for RISC-V builds
- Use a BigSky-class development server for performance profiling
- Track standardized platform profiles from Hot Chips 2026 announcements
- Watch CUDA-on-RISC-V progress if you rely on GPU acceleration
- Consider edge and LoRa-connected devices like the LilyGo K230 for IoT pilots
- Budget for longer debugging cycles — the tooling is younger than x86 or ARM
The economics favor early movers. Porting costs drop as platforms standardize.
Frequently Asked Questions
Which CPython version supports RISC-V?
CPython, the reference implementation of the Python programming language, has officially added support for the RISC-V CPU instruction set, as reported by PBXScience. This means the standard interpreter builds and runs on RISC-V hardware without community-maintained patches. Check the official CPython changelog for the exact release that first shipped the port.
Can you run CUDA workloads on RISC-V servers today?
Yes, in a development context. SiFive’s BigSky rackable server ships with NVIDIA CUDA running on the platform, according to Converge Digest. Chips and Cheese additionally reported from Hot Chips 2026 that NVIDIA is targeting broader CUDA support for RISC-V, though terms and conditions may apply.
What is SiFive BigSky and who is it for?
BigSky is a 2U rackable RISC-V datacenter development server powered by 32 P870-D cores, with enterprise Linux support. The Register describes it as intended for software porting and workload optimization ahead of wider datacenter adoption. It targets developers and enterprises preparing their stacks for open-ISA infrastructure.
Are there affordable RISC-V computers for hobbyists?
Yes. Open Source For You reported on KEO, an affordable AI-enabled PC built on RISC-V, Ubuntu Linux, and open-source software. On the ultra-portable end, Notebookcheck covered the LilyGo K230, a RISC-V handheld with an optional keyboard and LoRa support for off-grid communication without Wi-Fi or cellular networks.
Summary
- CPython’s official RISC-V support means the reference Python interpreter now runs on the open ISA, lowering the barrier for software porting.
- SiFive’s BigSky — a 2U server with 32 P870-D cores, enterprise Linux, and CUDA — gives developers real rack hardware to port and optimize against.
- NVIDIA targeting CUDA at RISC-V, as seen at Hot Chips 2026, could pull the entire GPU-accelerated Python ecosystem toward the open ISA.
- Custom extensions remain RISC-V’s differentiator and its fragmentation risk; standardized platform profiles are the industry’s answer.
- Affordable machines like the KEO desktop and LilyGo K230 handheld make hands-on RISC-V experimentation cheap and practical.
If you write Python, now is the time to spin up a RISC-V build target and see what breaks. Read the CPython release notes, browse the BigSky documentation, and subscribe for more coverage of open-architecture computing.